help with cache mistakes

i need help to get the right correct answers for my homework: This is very hard to read, and is lacking structure FYI: n-way set associative == n Blocks/Set # of sets = (Total Storage in Bytes ÷ # Bytes/block) ÷ (# of Blocks/Set) Offset bits = Log(base 2) of (# of Bytes/block) Index bits = Log(base 2) of (# of Sets) Tag bits = 32 – (Offset bits + Index bits) Cache hit is where requested address Tag == Stored Tag at the corresponding Index AND Valid bit == 1 Errors: -10 1a. Addresses are 32 bits not 12; Index bits listed are wrong; 26 Tag bits; the “Hits” you listed are wrong. -15 1b. Addresses are 32 bits not 10; Errors in offset bits = Log(base 2) of (# of Bytes/block) = 3; Index bits listed are wrong; 26 Tag bits; none of the “Hits” you listed are correct. -3 2. c. 1.09 = (32*8+2+22)/(32*8) -5 3.a. The final state of the cache has several errors. Your “Allocation in pages” should be “DRAM Base Address”. You are missing the Tag values in in the Cache table. HIT == requested address Tag == Stored Tag at the corresponding Index AND Valid bit == 1; Where are you getting “Page no”? ;There is NO mention of “Page Numbers” with respect to Cache. I think you were trying to identify the DRAM Block address. The beginning of the DRAM Block address is 32 bits where the offset bits are set to “0”. Address: 1012 –> 0x000003F4 –> 0000 0000 0000 0000 0000 0011 1111 0100 –> Block address = 0000 0000 0000 0000 0000 0011 1111 0000 –> 0x000003F0 –> 1008 == 126 * 2^3 (shifting your value left 3 bits) -20 3.b. Completely missing

this the comment of that needed to be fix

Please don’t use Chegg since it has wrong respond